The present invention relates generally to network storage systems and memory controller architecture and more specifically to a method and system to eliminate race conditions in memory controller architectures.
The utilization and expansion of computer technology has increased the necessity of inexpensive and reliable data storage. One example of inexpensive and reliable data storage is the Redundant Array of Inexpensive Disks (RAID) system. RAID implementations enhance the reliability and integrity of data storage through the redundant writing of data across a given number of physical disks.
In the past, peripheral component interconnect (PCI) internal busses were utilized for RAID array controllers. PCI busses perfomed well in that they could operate without creating memory race conditions by producing an immediate write operation that could be completed in a short period of time. However, the utilization of PCI busses is accompanied by a limited amount of bandwidth and difficulty in expansion. Other types of internal architectures are now being utilized to transport data between processors and input/output devices such as INFINIBAND which allow greater bandwidth and easier expansion. A problem with internal architectures other than PCI for RAID controllers is race conditions whereby undesirable results may occur due to the critical dependence on the relative timing of events.
Accordingly, the present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. In one embodiment of the invention, a system of the present invention may include a memory controller which may delay an acknowledgment to a requester until the resulting memory operation has been completed. In another embodiment of the invention, a method of the present invention may provide remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.